Re: Cine CPU gate complexity

From: Clay Cowgill <clay_at_supra.com>
Date: Thu Jun 26 1997 - 16:08:29 EDT

> Another problem might be I/Os. I think Steve O. told me that he
>had tried to do an FPGA based design, but there were too many I/Os for it
>to fit on 1 FPGA. Chances are it'll take 2 or 3 "big" ones (It's been
>about 2 years since I touched an FPGA, so I don't know what the "big" ones
>are nowadays.)

That was the problem I had with moving the Atari Vector Generator to FPGA.
I wanted to be in the $16 range (singles) and didn't have enough I/O's on
much of anything.

Supposedly Xilinx has some new stuff coming out that's much cheaper than
before and with better I/O capacity. They're coming by to see us in the
next couple days, so I'll grab the databooks and whatnot. Phillips have
been trying pretty hard to get our attention on FPGA stuff recently too--
they have a lot of Lucent look-alike stuff...

-Clay

Clayton N. Cowgill Engineering Manager
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Received on Thu Jun 26 12:06:22 1997

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