(no subject)

I just played human OCR, and typed in the two page vector generator
description, that I was talking about in the last message. I also
noticed that the G-08 schematics show Motorola deflection transistors
(MJ15003/MJ15004 PNP/NPN pair) instead of the pair of 2N6259 NPN's.

MJ15003's are rated at 20A 140V 250W. max

This is really weird.. The G08-003 is marked in this manual as
"for future reference". They changed the outputs from a PNP-NPN
pair to a pair of NPN's, but kept the part number the same?

Mouser has the MJ15003's listed at around 6.50 ea. < 10.

G-80 Control and Timing Boards Operation, Detailed

Note: Designations in parentheses will be used throughout this
discussion to refer the reader to the proper schematics. C =
X-Y Control Board #800-0163, sheets 5 and 6. T = X-Y Timing Board
#800-0161. sheets 5, 6, and 7. e.g. (C6) = Control Board, sheet 6.

 The CPU addresses video memory, U24-U31, through multiplexer ICs
U48 and U49 (C5). Character words are taken from memory as the
Program Counter, ICs U33, U34, U22 (C5), addresses them through
mulitplexers U36, U49, U35, and U21 (C5). If Word 1 (Symbol
Instructions) says to not display a symbol, the Program Counter is
advanced 10 counts by U33, a full adder, which adds 10 to the counter
when signal ADD goes low. The Vector Address counter is composed of
U10, U11, and U12 (C5) and is loaded with the first address of the
Line Instructions from video memory's Character Data Bus, CD0-CD7.
The CPU's Data Bus, D0-D7, is brought to the memory through a
bi-directional buffer, U14 (C5). The signal labelled FETCH (c5)
latches the various Character Data words from memory. The MUX (C5)
signal commands the multiplexer ICs to allow either the CPU, Program
Counter or Vector Address counter to address memory. MEMR (memory
read) and MEMW (memory write) come from the CPU board to read from
or write to the RAM. Signal VCE (C5) Vector Clock Enable, increments
the Vector Address counter. PCC (Program Counter Clock) is the string
of pulses that advances the Program Counter; PCR (Program Counter
Reset) ensures that the Program Counter starts counting at the first
location in video RAM each time PCR goes low. This signal occurs first
at power-up and then 40 times a second during program execution. So,
it causes the X-Y monitor to draw and re-draw each symbol on the screen
40 times a second.

 The signal is generated from the master clock (crystal Y1 and U14, T7)
by U31-U34 and U22 (T7). The other clock signals (VCE, PCC, FETCH, ADD,
MUX, and VCL) are all generated by the X-Y timing board (T7).
The outputs of the Last Symbol and Last Vector latches (U52, T7) are
AND'd together with the signal END, which originates from the Control
Board's U18 (C6). When U18's output goes low, it signifies that no more
symbols are to be drawn. Then, the Program Counter is reset by the 40 HZ
signal to the start of the video memory to repeat the display sequence.
U22 (T7) is the DRAW latch and its output, through U21, creates the DRAW
signal which initiates a sequence that causes the beam to draw. This
sequence occurs on the Timing Board, sheet 6: By this time, all video
words have been stored in their proper places in the system. On the
Timing Board (T7), the vector angle is in U56, the symbol angle is U55.
So, when the DRAW goes high, it causes strings of digitial pulses that
represet the vector and symbol angles to be generated. These streams of
pulses (from U28, T6) are the ones that clock the X and Y Up/Down
counters, shown on T5 (U15-U20). U25 (T6) tells the counters in which
direction to count, up or down (D/UX, D/UY). Then the outputs of the
Up/Down counters, X and Y, become the digital words that are converted
to analog signals by D/A converters U1 and U4 (T5). Op Amps U2 and U3 (T5)
convert current from the D/A converters to voltage levels. These levels
drive the Vertical and Horizontal inputs to the monitor. Signals DRAW and
VCL are combined in U28 (T6) to form DCL (Draw Clock). This signal clocks
down the Vector Length counters U15, U16 and U17 (C6) which contain words
that represent various lengths of the lines to be displayed. When the
counters have counted down to 0, the END signal becomes active. As the X
and Y Up/Down counters are clocked, their outputs are sensed by U5-U10 (T5)
which are multiplexers. The multiplexers are necessary to tell the system
when the beam is off the screen. It does this by generating the BOS signal
(T5). Then BOS is AND'd with DRAW at U5 (C6), to blank (turn off) the beam
whenever BOS goes low.

 U3 (C6) compesnsates for the inherent delay in delflecting the electron
beams. It provides a number of taps to select a range of delay times. From
U2 (C6), the color word is read and applied to the RGB D/A converters U5,
U1, and associated diodes and resistors. The RGB outputs go directly to the
color X-Y monitor.

 U50, a 74LS154 (T7) decoder IC, selects one of 15 outputs by making the output
low. The outputs sequentially store the video memory words, one at a time, in
various parts of the X-Y boards. Only one output is allowed to go low at a
time. U50 is enabled at pin 18, fourty times per second by U22 (T7), and at
pin 19 by U21. U51 sequences U50 through its 15 count cycle; at count 14, pin
16 of U50 goes low to initiate the DRAW signal through U40, U21 and U22 (t7).

 The circuitry at the top of schematic C6 (U45, U51-U54) is not used in
generating and displaying characters on the X-Y monitor. Its function is to
perform lengthy calculations under software control.
Received on Sun Aug 24 11:03:38 1997