Re: PC Vector-generator card

From: Clay Cowgill <clayc_at_diamondmm.com>
Date: Tue Dec 09 1997 - 15:14:49 EST

>Actually I do care, I'm just under massive pressure until late wednesday to get
>out a demo of the project I'm working on.

Ahhh, I understand. I'm generating milestone dates for my group in
Microsoft Project as we speak... Ewwww. I'm being managerial. ;-)

>I have some ideas to bounce off you as far as putting a Bresenham's line draw
>engine into hardware.

That would be very cool. I had been looking into this myself a bit--
trying to decide what optomizations to Bresenham's make sense for vectors.
(Alas, line symmetry is probably a no-go.) Bresenham's stuff looks easier
in VHDL than in schematic entry to me at lease... Just need to talk the
local reps out of the VHDL package!

>It looks easier to me than the rate multipliers and the
>real nice thing is that it can be setup (very easily) to be self clocking --
>that is different angle lines will always be drawn at a constant rate.

That would be nice. From what I can tell, it looks like the "classic"
Bresenham's algorithm is about 16 instructions or so for most processors.
I just couldn't figure out how to get the speed needed for even "asteroids"
level performance from any commonly available processor... The constant
rate draw looked daunting to me though. You'll have to educate me. ;-)

>And
>being a Bresenham line draw, there is no accumulative error. (Those lines will
>always match at the end points)

That'd be cool. I was a little cautious about how well I could get things
to line up with the rate multipliers, but I think if the step size is small
and the line counter is clocked with the BRM's it'd be pretty close.

>Give me until the end of the week and I'll come up with a little block
>diagram/schematic sort of thing to show you what I mean. It's actually simple,
>I just have *zero* time right now.

No problem. I'll still be tinkering with it I'm sure. (I'm pretty proud
of the BRM's actually-- did it all using the "generic" HDL symbols so
they'll target to pretty much any FPGA/CPLD/kinda thing. I'll probably
have to wire-wrap a socket for the Lattice part and try the
in-circuit-programming feature. Hack it onto an Asteroids board and see if
it works. ;-)

>(Back to work, I just got a call for a progress report -- *crack* goes the
>whip!)

Me too, gotta commit to some ship dates. *sigh*

-Clay

Clayton N. Cowgill Engineering Manager
_______________________________________________________________________
/\ Diamond Multimedia Systems, Inc. clay@supra.com
\/ Communications Division http://www.supra.com/
Received on Tue Dec 9 12:13:42 1997

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