Re: Dumb EE question

From: <solarfox_at_texas.net>
Date: Tue Apr 24 2001 - 20:59:07 EDT

On Tue, 24 Apr 2001 17:14:48 -0700 (PDT), you wrote:

>A B | O
>-------
>0 0 | 0
>0 1 | 1
>1 0 | 0
>1 1 | 0
>
>Is there a simple logic gate that will generate this output? Please don't
>say PAL... I don't have a programmer. ;-(

        Oh, god, no... a PAL would be _way_ overkill for this! (Frankly, I'd
fire any engineer who's first instinct was to use a PAL for such a simple
logic...)

>But if it could be done with standard gating fairly easily, let me know!

        Ask and ye shall recieve: :)

     1/6 7404
       1|\ 2 _____
A ------| >O-----| \
        |/ 1 | 1/4 |______ O
                 | 7408 |3
B ---------------|_____/
               2

        (Substitute appropriate logic family for the job at hand. :) ) Or, if
you don't mind a little extra propagation delay and would rather do it in a
single chip, then you can do this:

         _____
      _1| 1/4 \ 4 _____ _____
A ---|__| 7400 |O--------| 1/4 \ _9| 1/4 \ 8
       2|_____/ 3 ___| 7400 |O-----|__| 7400 |O-----
                     | 5|_____/ 6 10|_____/
B -------------------

-----------------------------------------------------------------------------
"There is no virtue in suffering fools gladly, for it only encourages them to
persist in their foolishness." --Kehlog Albran
-----------------------------------------------------------------------------
solarfox@DON'TMESSWITHtexas.net (Gary Akins jr.)
http://lonestar.texas.net/~solarfox
-----------------------------------------------------------------------------
---------------------------------------------------------------------------
** To UNSUBSCRIBE from vectorlist, send a message with "UNSUBSCRIBE" in the
** message body to vectorlist-request@synthcom.com. Please direct other
** questions, comments, or problems to neil@synthcom.com.
Received on Tue Apr 24 21:09:06 2001

This archive was generated by hypermail 2.1.8 : Thu Jul 31 2003 - 23:00:51 EDT