Re: The chicken or the egg?

From: Rodger Boots <rlboots_at_cedar-rapids.net>
Date: Sun Oct 13 2002 - 02:11:40 EDT

Travis Shire wrote:

>Hey guys,
>
>Going through a stack of dead asteroids bds today I came across a rather odd vector gen problem (mpu is ok). There is no clk getting to the data latches so they're not doing what they should, and the timer 0-3 lines (from one of the latches) are required by the state machine for it to operate. Now if the latch signals are supplied at the vsm, it seems to me like a catch-22. Am I overlooking something here?
>
>Travis
>

Possibly. Reset should force Timer 0, 1, 2, & 3 low. Are they going low?

So that means the PROM (at C8) pins 1-3 are forced low by a reset. As
long as reset is happening ALL the outputs of the 74LS42 should stay
high and HALT should be high. After RESET goes away HALT should go low
and the state machine should run (as long as there's a clock at the
74LS174 (at D8) pin 9) and the 74LS42 should output something somewhere
whenever pin 12 goes low.

Of couse the PROM could be bad.

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Received on Sat Oct 12 23:14:05 2002

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