Re: Cinematronics CCPU on Xilinx FPGA

From: Chris Leyson <cleyson_at_aol.com>
Date: Fri Apr 10 2009 - 10:32:53 EDT

Apologies for not replying to all those who kindly posted replies, I've been a little distracted getting the bugs out of the CCPU. Actually, obsessed is more accurate :)
It's really rewarding to see a lot of interest and enthusiasm in the project.  Who knows, it could lead on to further things, but more about that later. 

I'm reasonable confident in the CCPU model, I've added an IIR filter to simulate the RC network and run through a few frames of Spacewar. Plotting the vector start
and end points in a spreadsheet gives me the start-up screen :). Where are my spaceships !! Damn, haven't done the I/O yet, so no coin input :)  Grrrrr
Next step is to clean up the clocking and register some of the glitchy logic.

So, here goes, some replies...

Ed Henciak wrote:

Freakin' sweet :-)!  Your best QoR for area is going to be the gate level approach you are taking.  The
tradeoff is "time to implement" in most cases.

Also, keep in mind that a behavioral design means exactly what it says...it doesn't mean it is synthesizable.
Moreover, if anyone tells you one way is better than another they are nuts.  The example I sent you is more
abstract (i.e. RTL)...what's cool is that XST seems to do a decent job converting what I am "implying" when
I view the design using post-synthesis viewers.  Still, area-wise, it will be no match to your results.  For
designs like the CCPU, gate level is the way to go....I prefer the RTL approach since that's simply the way
I do things :-)!

I'm more a a "nuts and bolts" guy and would rather follow a schematic, but it all boils down to RTL at the end of the day.

Just a suggestion....goto www.fpgaarcade.com ... there is an Asteroids-on-a-chip package.  In there,
MikeJ has a vector-to-VGA converter.  You will need to add a ZBT SRAM model to your design.
You might be able to pump out some graphics....just be aware that what you see in simulation may not
match expected results graphics wise :-)! 

What version of Modelsim are you using BTW?

Damn that's cool. That'll definitely be the next project, vectors to VGA or PAL, NTSC or HDMI.
PAL/NTSC is easy but HDMI is the way to go. ModelsimXE, the freebee.

Ed Henciak wrote:

Actually, it'd fit comfortably in a dirt cheap Spartan 3e (tiniest one) with room to spare :-)!  I was
thinking about using the left over gates for an embedded CPU to drive a kick ass menu system
for the CCPU.

I sent Zonn most of my code a while back...I've been trying to find time to finish this off once and
for all.  Quite honestly, if someone can help me with verification, I think we all can have a nice
VHDL model of the CCPU :-)!I basically have coding finished (I need to add the vector draw routines),
but I still want to make a solid testbench to verify the hell out of this thing.

Will gladly help with the verification, I guess if we sync on reset we could run two implementations together and
xor test vectors to spot any differences.

   A while back I put the Atari 2600 into an FPGA using that Opencores 6502...it's sheer joy to cycle-for-cycledebug a flaky 6502 core :-)!
I think we can do some neat tricks with Zonn's emulator and a VHDL simulation though.

Arghhh..... There are too many flaky cores out there. I like to see block ram microcoded implementations of old 8 bitters.
Wow.. 2600 on a chip, excellent !! Yet another project I'd like to do but haven't had the time.  Really like the Atari 2600
games but the poor video quality lets the old consoles down, too much digital crap leaking into the video.

One of the smaller Actel parts might be able to fit the CCPU as well....I can run it thru Synplify in a minute here
to get a gate count...nice thing about them is that they run from a single 3.3V source if I am not mistaken.
Also, you can do neat tricks like run the XY outputs to a single DAC with dual outputs.  I would need help with
the amplification part (I know there are analog gurus on this list that can make the "perfect, clean" vector driver :-) ).

I'm aiming to use Spartan 3 for the CCPU , no Actel design experience,  so will go for Xilinx primatives in my design.
Agreed, DACs will have to be fast, preferably serial, but will require the analogue switch and RC network, this is
the best option for smooth vectors. The digital approach on the other hand wouldn't need the RC integrator but
would need faster, higher resolution DACs, not exactly cost effective.

Ed

PS If people are *really* interested, I will post what I have here on Vectorlist...I just don't know the protocol
for posting these kinds of things :-)!  But I'd LOVE to see this project completed.  It's just two text files of
VHDL source.  I don't have a webpage or anything...but I'd prefer to keep it amongst us vectorheads for the
time being :-)!

Agreed, will post what I have done to date, but where ??

Omar Vega wrote:

Hey Chris,

Just in case you have more time these days than I do, it will synthesize
into a pretty small part (think spartan II < 100k gates, 50k IIRC).  I had a
nice simulation running (starhawk roms) but mine hangs up after about 130 ms
or roughly a couple of full frames of drawing vectors (PITA debug).  I agree
that Zonn's simulator is usefull for getting started and so is his
disassembler. 
Omar

Thanks for the simulator screen shots. It looks as if some of your sequencer logic is halting whilst drawing.
I will try out Starhawks roms and see how it compares.

Chris Schalick wrote:

I got started on a Verilog CCPU a while ago, with the same 
structural approach.  I got through a thousand instructions 
or so till it went red on me, summer showed up and I lost track of it.

Much to my wife's chagrin, I speak Vhdl and would be happy to 
help verify if you want help.

Chris
    

Hi Chris, sorry I can't speak Verilog, but I'm happy to send you what I've done so far so you can
debug the Verilog.

On this note, it's probably a good idea if I sat down and wrote out a few timing diagrams for different
opcode formats, both for even and odd rom addresses.

Chris

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