Re: Asteroids Troubleshooting.

Wasn't there a simple way to disable one VG Ready line (or whatever it was) - So that the CPU would run blind, and you could determine if the VG was faulty or the CPU side of things ? - I'm sure its in the asteroids trouble shooting guide on line somewhere....

Cheers, Colin
  ----- Original Message -----
  From: Kevin Moore
  To: vectorlist@vectorlist.org
  Sent: Sunday, January 10, 2010 6:29 PM
  Subject: VECTOR: Asteroids Troubleshooting.

  I'm still trying to learn all this, so please bare with me. Basically I'm trying to figure out the best way to troubleshoot Asteroids boards. It shouldn't be as difficult as I'm making it out to be, or is it?

  Ok I've got several asteroids boards with the same symtoms.

  Test mode comes up good.
  No Ram errors, No rom errors.
  But under normal game play, get constant reset on pin 40of the CPU

  Currently just trying to learn how to trouble shoot 1 board, so I haven't done all these test on the rest yet.

  Have done the following
  Verified Rom sigs with Fluke
  Verified Ram with Fluke
  Verified Bus with Fluke
  Have written the following AVG test program to get + sign with Fluke
  And well I get the + Sign.

  WRITE @ 4000 = FF
     WRITE @ 4001 = A3
     WRITE @ 4002 = 00
     WRITE @ 4003 = 02
     WRITE @ 4004 = FF
     WRITE @ 4005 = 97
     WRITE @ 4006 = 00
     WRITE @ 4007 = 90
     WRITE @ 4008 = 00
     WRITE @ 4009 = A2
     WRITE @ 400A = 00
     WRITE @ 400B = 00
     WRITE @ 400C = 00
     WRITE @ 400D = 90
     WRITE @ 400E = FF
     WRITE @ 400F = 33
     WRITE @ 4010 = 00
     WRITE @ 4011 = E0
     DPY-CONFIRM PLUS PATTERN. CONT#
     DPY-+=EXIT%1#
  0: LABEL 0
     WRITE @ 3000 = 00
     IF REG1 = 25 GOTO 2
     GOTO 0
  2: LABEL 2
     DPY-##

  Went ahead and did sig analysis with the catbox to double check the address lines, and data lines.
  Ran Sig analysis on the VG Address selector,and address generator.

  I'm assuming since the sigs are good for those two areas, that the VG program counter is functioning correctly?

  I don't have sigs for the vector generator buffer, I'll have to work on that since I have several revision boards, some with R2, and some with P2. But I'm getting out what is going in, so I assume the buffer is ok.

  So that leaves the VG Memory data latches? Specifically K7, and J7?

  Does that sound about right, or am I just not getting it..

  Thanks,

  Kevin

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Received on Sun Jan 10 16:43:42 2010