Cinematronics Watchdog Timer Circuit?

From: Jason Sullivan <>
Date: Sat Feb 06 2010 - 14:37:34 EST

So after a long hiatus during which I managed to get gainfully
employed and stuff, I got back to work on the Cinematronics CPU in
Verilog. I'm using MAME as a "known good" model and comparing program
flow between MAME and my model. It looks good so far, but I'm having
problems with the watchdog timer.

According to the documentation I have (it's for the Armor Attack
game), the timer runs on a cycle of 26.5ms with a 15% duty cycle. It
appears that that's what's happening (assuming it's a 15% low duty
cycle, waveform attached). The other docs say that the timer should
tick _twice_ before a reset happens, which is most decidedly not

Can anyone with knowledge of the motherboard provide some insight as
to what might be going on. I think the intent of the AND gate that's
right after the first JKFF that latches !proceed is to take the
latched first version of !proceed and and it with !proceed, but the
circuitry won't do that as specified in the schematics.

Anyone know for sure how this is supposed to work? Thanks in advance.

Jason Sullivan

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Received on Sat Feb 6 14:48:31 2010

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