I just dug around the net and found an on line description of the
6551 ACIA, which should just drop onto the cat box's 6502 bus. That,
a 3.6mhz crystal and a max232 will give you an RS232 interface.
APPENDIX: 6551 ACIA HARDWARE SPECS (DATA SHEET)
C= Commodore Semiconductor Group
a division of Commodore Business Machines, Inc.
950 Rittenhouse Road, Nornstown, PA 19400 * 215/666-7950 * TWX 510-660-4168
(July 1987)
6551 ASYNCHRONOUS COMMUNICATION INTERFACE ADAPTER
CONCEPT:
The 6551 is an Asynchronous Communication Adapter (ACIA) intended to provide
for interfacing the 6500/6800 microprocessor families to serial communication
data sets and modems. A unique feature is the inclusion of an on-chip
programmable baud-rate generator, with a crystal being the only external
component required.
FEATURES:
* On-chip baud-rate generator: 15 programmable baud rates derived from a
standard standard 1.8432 MHz external crystal (50 to 19,200 baud) [these
rates are doubled in the SwiftLink].
* Programmable interrupt and status register to simplify software design.
* Single +5 volt power supply.
* Serial echo mode.
* False start bit detection.
* 8-bit bi-directional data bus for direct communication with the
microprocessor.
* External 16x clock input for non-standard baud rates (up to 125 Kbaud).
* Programmable: word lengths; number of stop bits; and parity-bit generation
and detection.
* Data set and modem control signals provided.
* Parity: (odd, even, none, mark, space).
* Full-duplex or half-duplex operation.
* 5,6,7 and 8-bit transmission.
* 1-MHz, 2-MHz, and 3-MHz operation.
ORDER NUMBER
MXS 6551 ___
- |
| +---- Frequency range
| Plain = 1 MHz
| A = 2 MHz
| B = 3 MHz
|
+----------- Package Designator
C = Ceramic
P = Plastic
6551 PIN CONFIGURATION
+---------------+
GND --| 1 28 |-- R-/W
CS0 --| 2 27 |-- o2
/CS1 --| 3 26 |-- /IRQ
/RES --| 4 25 |-- DB7
RxC --| 5 24 |-- DB6
XTAL1 --| 6 23 |-- DB5
XTAL2 --| 7 22 |-- DB4
/RTS --| 8 21 |-- DB3
/CTS --| 9 20 |-- DB2
TxD --| 10 19 |-- DB1
/DTR --| 11 18 |-- DB0
RxD --| 12 17 |-- /DSR
RS0 --| 13 16 |-- /DCD
RS1 --| 14 15 |-- Vcc
+---------------+
BLOCK DIAGRAM +----------+
| TRANSMIT |
| CONTROL |<------- CTS
+----------+
|
v
+----------+ +----------+
| TRANSMIT | | TRANSMIT |
/|===>| DATA |=========>| SHIFT |-------> TxD
|| | REGISTER | | REGISTER |
|| +----------+ +----------+
+---------+ ||
o2 --->| | || +----------+ +----------+
R-/W --->| SELECT | ||====| STATUS | | INTERRUPT|-------> /IRQ
CS0 --->| AND | || | REGISTER |<-------->| LOGIC |<------- /DCD
/CS1 --->| CONTROL | || +----------+ +----------+<------- /DSR
RS0 --->| LOGIC | ||
RS1 --->| | || +----------+ +----------+
/RES --->| | ||===>| CONTROL | | BAUD-RATE|<------> RxC
+---------+ || | REGISTER | | GENERATOR|<------- XTAL1
|| +----------+ +----------+<------- XTAL2
||
+---------+ || +----------+ +----------+
DB0 <-->| DATA- | || | RECEIVE | | RECEIVE |
... | BUS |<===||====| DATA |<=========| SHIFT |<---+--- RxD
DB7 <-->| BUFFERS | || | REGISTER | | REGISTER | |
+---------+ || +----------+ +-----.----+ |
|| | |
|| +----------+ +----------+ |
LEGEND: \|===>| COMMAND | | RECEIVE | |
| REGISTER | | CONTROL |<---+
===> : 8-bit line +----------+ +----------+
| |
---> : 1-bit line | +--------------------------------> /DTR
+-------------------------------------> /RTS
MAXIMUM RATINGS
<not included here>
ELECTRICAL CHARACTERISTICS
<not included here>
POWER DISSIPATION vs TEMPERATURE
<not included here>
TIMING CHARACTERISTICS
<not included here>
INTERFACE SIGNAL DESCRIPTION
/RES (Reset)
During system initialization a low on the /RES input will cause internal
registers to be cleared.
o2 (Input Clock)
The input clock is the system o2 clock and is used to trigger all data
transfers between the system microprocessor and the 6551.
R-/W (Read/Write)
The R-/W is generated by the microprocessor and is used to control the
direction of data transfers. A high on the R-/W pin allows the processor
to read the data supplied by the 6551. A low on the R-/W pin allows a write
to the 6551.
/IRQ (Interrupt Request)
The /IRQ pin is an interrupt signal from the interrupt-control logic. It is
an open drain output, permitting several devices to be connected to the common
/IRQ microprocessor input. Normally a high level, /IRQ goes low when an
interrupt occurs.
DB0--DB7 (Data Bus)
The DB0--DB7 pins are the eight data lines used for transfer of data between
the processor and the 6551. These lines are bi-directional and are normally
high-impedance except during Read cycles when selected.
CS0, /CS1 (Chip Selects)
The two chip-select inputs are normally connected to the processor-address
lines either directly or through decoders. The 6551 is selected when CS0 is
high and /CS1 is low.
RS0, RS1 (Register Selects)
The two register-select lines are normally connected to the processor-address
lines to allow the processor to select the various 6551 internal registers.
The following table indicates the internal register-select coding:
RS1 RS0 WRITE READ SL-Addr
--- --- ---------------------- --------------------- -------
0 0 Transmit Data Register Receive Data Register $DE00
0 1 Programmed Reset* Status Register $DE01
1 0 Command Register Command Register $DE02
1 1 Control Register Control Register $DE03
* for programmed reset, data is "don't care".
The table shows that only the Command and Control registers are read/write.
The Programmed Reset operation does not cause any data transfer, but is used
to clear the 6551 registers. The Programmed Reset is slightly different from
the Hardware Reset (/RES) and these differences are described in the
individual register definitions.
ACIA/MODEM INTERFACE SIGNAL DESCRIPTION
XTAL1, XTAL2 (Crystal Pins)
These pins are normally directly connected to the external crystal (1.8432
MHz) used to derive the various baud rates. Alternatively, an externally
generated clock may be used to drive the XTAL1 pin, in which case the XTAL2
pin must float. XTAL1 is the input pin for the transmit clock.
TxD (Transmit Data)
The TxD output line is used to transfer serial NRZ (non-return-to-zero) data
to the modem. The LSB (least-significant bit) of the Transmit Data Register
is the first data bit transmitted and the reate of data transmission is
determined by the baud rate selected.
RxD (Receive Data)
The RxD input line is used to transfer serial NRZ data into the ACIA from the
modem, LSB first. The receiver data rate is either the programmed baud rate
or the rate of an externally generated receiver clock. This selection is made
by programming the Control Register.
RxC (Receive Clock)
The RxC is a bi-directional pin which serves as either the receiver 16x clock
input or the receiver 16x clock output. The latter mode results if the
internal baud rate generator is selected for receiver data clocking.
/RTS (Request to Send)
The /RTS output pin is used to control the modem from the processor. The
state of the /RTS pin is determined by the contents of the Command Register.
/CTS (Clear to Send)
The /CTS input pin is used to control the transmitter operation. The enable
state is with /CTS low. The transmitter is automatically disabled if /CTS is
high.
/DTR (Data Terminal Ready)
The output pin is used to indicate the status of the 6551 to the modem. A low
of /DTR indicates the 6551 is enabled and a high indicates it is disabled.
The processor controls this pin via bit 0 of the Command Register.
/DSR (Data Set Ready)
The /DSR input pin is used to indicate to the 6551 the status of the modem. A
low indicates the "ready" state and a high, "not-ready". /DSR is a high-
impedance input and must not be a no-connect. If unused, it should be driven
high or low, but not switched.
Note: If Command Register Bit #0 = 1 and a change of state on /DSR occurs,
/IRQ will be set and Status Register Bit #[5] will reflect the new level. The
state of /DSR does not affect Transmitter operation [but must be low for the
Receiver to operate]. [This statement reflects the SwiftLink implementation].
/DCD (Data Carrier Detect)
The /DCD input pin is used to indicate to the 6551 the status of the carrier-
detect output of the modem. A low indicates that the modem carrier signal is
present and a high, that it is not. /DCD, like /DSR, is a high-impedance
input and must not be a no-connect.
Note: If Command Register Bit #0 = 1 and a change of state on /DSR occurs,
/IRQ will be set and Status Register Bit #[6] will reflect the new level. The
state of /DCD does not affect either Transmitter or Receiver operation.
INTERNAL ORGANIZATION
<not included here>
TRANSMIT AND RECEIVE DATA REGISTERS (SL-Addr: $DE00 / 56832)
These registers are used as temporary data storage for the 6551 Transmit and
Receive circuits. The Transmit Data Register is characterized as follows:
* Bit 0 is the leading bit to be transmitted.
* Unused data bits are the high-order bits and are "don't care" for
transmission.
The Receive Data Register is characterized in a similar fashion:
* Bit 0 is the leading bit received.
* Unused data bits are the high-order bits and are "0" for the receiver.
* Parity bits are not contained in the Receive Data Register, but are stripped
off after being used for external parity checking. Parity and all unused
high-order bits are "0".
Transmit / Receive Data Register
+-----+-----+-----+-----+-----+-----+-----+-----+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-----+-----+-----+-----+-----+-----+-----+-----+
| data |
The following figure illustrates a single transmitted or received data
word, for the example of 8 data bits, parity, and 1 stop bit:
"MARK"____ ___________________________________________________"MARK"
| | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | P | S .
|____|____|____|____|____|____|____|____|____|____|
start parity stop
bit ...data bits... bit bit
STATUS REGISTER (SL-Addr: $DE01 / 56833)
The Status Register is used to indicate to the processor the status of various
6551 functions and is outlined here:
Command Register
+-----+-----+-----+-----+-----+-----+-----+-----+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-----+-----+-----+-----+-----+-----+-----+-----+
| irq | dcd | dsr | txr | rxr | ovr | fe | pe |
+---+
| 7 | /IRQ*** : cleared by reading status register
+---+ --------------------------------------------
0 No interrupt
1 Interrupt
+---+
| 6 | /DCD : non-resetable, indicates /DCD status
+---+ --------------------------------------------
0 /DCD low
1 /DCD high
+---+
| 5 | /DSR : non-resetable, indicates /DSR status
+---+ --------------------------------------------
0 /DSR low
1 /DSR high
+---+
| 4 | Transmit Data Register Empty: Cleared by write to Tx Data reg
+---+ -------------------------------------------------------------
0 Not empty
1 Empty
+---+
| 3 | Receive Data Register Full: Cleared by read from Rx Data reg
+---+ -------------------------------------------------------------
0 Not full
1 Full
+---+
| 2 | Overrun*: Self-clearing**
+---+ -------------------------
0 No error
1 Error
+---+
| 1 | Framing Error*: Self-clearing**
+---+ -------------------------------
0 No error
1 Error
+---+
| 0 | Parity Error*: Self-clearing**
+---+ ------------------------------
0 No error
1 Error
Notes: * No interrupt generated for these conditions
** Cleared automatically after a read of RDR and the next error-
free receipt of data
*** Reading status reg. will clear the /IRQ bit except when
transmit intr. enabled
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
| 0 | x | x | 1 | 0 | 0 | 0 | 0 | After Hardware reset
+---+---+---+---+---+---+---+---+
| x | x | x | x | x | 0 | x | x | After Software reset
+---+---+---+---+---+---+---+---+
COMMAND REGISTER (SL-Addr: $DE02 / 56834)
The Command Register is used to control specific Transmit/Receive functions
and is shown here:
Command Register
+-----+-----+-----+-----+-----+-----+-----+-----+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-----+-----+-----+-----+-----+-----+-----+-----+
| parity | echo| tx ctrl | rxi | dtr |
+---+---+---+
| 7 | 6 | 5 | PARITY CHECK CONTROLS
+---+---+---+ ----------------------
x x 0 parity disabled--no parity bit generated or received
0 0 1 odd parity receiver and transmitter
0 1 1 even parity receiver and transmitter
1 0 1 mark parity transmitted, parity check disabled
1 1 1 space parity transmitted, parity check disabled
+---+
| 4 | NORMAL/ECHO MODE FOR RECEIVER
+---+ ------------------------------
0 Normal
1 Echo (bits 2 and 3 must be "0")
+---+---+
| 3 | 2 | Tx INTERRUPT RTS LEVEL TRANSMITTER
+---+---+ ------------ --------- ------------
0 0 Disabled High Off
0 1 Enabled Low On
1 0 Disabled Low On
1 1 Disabled Low Transmit BRK
+---+
| 1 | RECEIVE INTERRUPT ENABLE
+---+ -------------------------
0 /IRQ interrupt Enabled from bit 3 of Status Register
1 /IRQ interrupt Disabled
+---+
| 0 | DATA TERMINAL READY
+---+ --------------------
0 Disable Receiver and all interrupts (/DTR high)
1 Enable Receiver and all interrupts (/DTR low)
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | After Hardware reset
+---+---+---+---+---+---+---+---+
| x | x | x | 0 | 0 | 0 | 0 | 0 | After Software reset
+---+---+---+---+---+---+---+---+
CONTROL REGISTER (SL-Addr: $DE03 / 56835 / cpm: 0001xxxx)
The Control Register is used to select the desired mode for the 6551. The
word length, number of stop bits, and clock controls are all determined
by the Control Register, which is shown here:
Control Register
+-----+-----+-----+-----+-----+-----+-----+-----+
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+-----+-----+-----+-----+-----+-----+-----+-----+
|stops| word len | src | baud rate |
+---+
| 7 | STOP BITS
+---+ ----------
0 1 stop bit
1 2 stop bits
1 1 stop bit if word length== 8 bits and parity
this allows for 9-bit transmission (8 data bits plus parity)
1 1.5 stop bits if word length== 5 bits and no parity
+---+---+
| 6 | 5 | WORD LENGTH
+---+---+ ------------
0 0 8 bits
0 1 7 bits
1 0 6 bits
1 1 5 bits
+---+
| 4 | RECEIVER CLOCK SOURCE
+---+ ----------
0 external receiver clock
1 baud rate generator
+---+---+---+---+
| 3 | 2 | 1 | 0 | BAUD RATE GENERATOR
+---+---+---+---+ --------------------
0 0 0 0 16x external clock
0 0 0 1 100 baud
0 0 1 0 150 baud
0 0 1 1 219.84 baud
0 1 0 0 269.16 baud
0 1 0 1 300 baud
0 1 1 0 600 baud
0 1 1 1 1200 baud
1 0 0 0 2400 baud
1 0 0 1 3600 baud
1 0 1 0 4800 baud
1 0 1 1 7200 baud
1 1 0 0 9600 baud
1 1 0 1 14400 baud
1 1 1 0 19200 baud
1 1 1 1 38400 baud
7 6 5 4 3 2 1 0
+---+---+---+---+---+---+---+---+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | After Hardware reset
+---+---+---+---+---+---+---+---+
| x | x | x | x | x | x | x | x | After Software reset
+---+---+---+---+---+---+---+---+
Received on Fri Jan 9 11:58:10 1998
This archive was generated by hypermail 2.1.8 : Fri Aug 01 2003 - 00:31:05 EDT