At 01:04 PM 1/18/99 -0600, you wrote:
>On Mon, 18 Jan 1999, Anders Knudsen wrote:
>
>> A reason the faster 2114 may be due to faster setup/hold times of the ram.
>> That is, now you have a ram chip with a faster setup time, but more
>> importantly in this case a faster hold time. So if the hold time is too
>> fast, the data out may not be on the bus for a long enough time for other
>> devices on the data bus. I havn't looked at the schematics, but it's
>> conceivable that one could replace the other devices with faster ones,
>> along with the faster rams, to compensate for the reduced hold times. It
>> should be easy enought to trace the ram data path and find which device(s)
>> (be they tri-state buffers, or whatever) are being affected by the reduced
>> hold time of the faster rams.
>>
>> -----------
>> a n d e r s
>>
>
> Maybe I totally missed what your were getting at though....
Maybe I was not very clear. What I meant is the SRAM Address change to Data
Out time. When the Address is changing, there is some time that the
previous output data is still valid before the next data propogates
through. Since the SRAM is now faster, the address to data out time is now
less, thus the data is not held on the bus for as long as it was for the
slower ram. This could be the problem with the faster SRAMs.
-----------
a n d e r s
Received on Mon Jan 18 13:13:08 1999
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