RE: AVG programming question...

> Sorry about taking so long to respond. I've been at home this week
> helping
> take care of our new little that was born on saturday.
>
Saturday! That was at least 4-5 days ago! Aren't they up and
self-sufficient by then? ;-) (Congrats, BTW!)

> When I first started writting space wars and tank.. (um forget about
> the
> second one, it's still secret) they worked great in MAME, but I had
> one heck
> of a time getting them to run on the real hardware. I now have them
> working
> almost 100% (just a few weird things still happening).
>
Must... resist urge... to bitch about... ...MAME. ;-) It saves me so
much time I won't grouse about it, but it definately doesn't model the
"real" hardware particularly religiously in a lot of ways...

> I don't know how similar tempest hardware is to space duel & gravitar,
> but
> this is how I got it to work.
>
> The ISR routine is completely independent of the vector drawing
> hardware and
> is used only for timing (I set my drawflag every 4th entry into the
> ISR)
>
Agreed. You might have come to the same timing conclusions I did.

> You must have a HALT instruction at the end of your vector list (0x20)
> or
> the vector generator won't release the VRAM back to the processor.
>
Yep, got that. (I actually init VRAM to 0x20 just incase I take a bad
JSR somewhere in the display list.)

> The halt
> instruction will also set the halt flag (on tempest it's 0x0C00 bit 6)
> which
> you should check before attempting to write anything to the VRAM.
>
Oh, S.O.B.!!! *THAT's* what that's for. Mother-$!@#$!@#$!!!! I saw
those and though it was trying to read the 3KHz stream. I must have
been off by a bit!

> The following routine should work
>
> zoom
> bit 0x0C00
> bvc zoom ;wait for vector generator to halt
>
Yeah! That's it. I actually have that inside my ISR. (I copied it
 from Tempest 'cause it was the only difference I could think was
different.)

> Timing
> lsr drawflag
> bcc Timing ;wait for timing flag
> dec 0x2002
> lda 0x2002
> cmp #0x18
> beq Done
> sta VGGO
> jmp zoom
> Done
>
Ahhh. Yeah, I can see how that works. The way my "works" is that the
ISR starts the VG, but I'll try to synchronize writes to VRAM outside of
the ISR by watching for the VGHalt. (My semaphore in the ISR was an
attempt to make a mock VGHalt signal since I was being an idiot and
didn't see the "real" one. ;-)

> plus you need something like this for your ISR
> ISR pha
> tya
> pha
> txa
> pha
> dec icount
> lda icount
> and #03
> bne ISR1
> inc drawflag ;set every 4th interrupt
>
Yeah, this looks pretty familiar. I do about the same thing, but update
some "other" stuff (decrement timers, etc) on non-drawing passes...

> ISR1 cli
>
Do you need that? Doesn't an RTI re-enable interrupts on the 6502?
> pla
> tax
> pla
> tay
> pla
> rti
>
> Also, I only use VGRESET once in the RESET routine and I use VGGO only
> in
> the main loop. That way the ISR won't fire it when you don't want it
> to go
> (and make all the VRAM unavailable)
>
True. I think I'll try to keep mine running async from the main code
though and just watch for the VG being ready. On the other hand,
letting the main loop

> I have a complete API for programming the Vector Generator, it
> currently
> works for space duel and gravitar and I've almost got it done for
> tempest. I
> also have an API for reading controls. All you have to do is change a
> compile flag and your code will run on another machine (with a few
> limitations, I don't have anything for accessing the mathbox in
> tempest and
> I'm still working on a DVG version of the VG API)
>
Cool. Sounds neat...

> Let me know if you have any other questions and if you want, you can
> shoot
> some of your code over to me and I can take a look at it (or course I
> would
> keep that confidential)
>
Ok, if I can't get it going in the next day or two I'll bug you. Just
being able to talk it over here is enough that I think I know where the
problem is. ;-)

Thanks,
-Clay
Received on Thu Apr 15 17:22:59 1999