Re: Z80

On Tue, 27 Jul 1999, jeff hendrix wrote:

> Is anybody on here an expert on the Z80?
> Specifically, how does the Z80 refresh dynamic memory?

I'm no expert, but I have a book:

(I'll use a trailing dash to indicate a bar over the signal name - active
low).

During clock periods T3 and T4 of the M1 (instruction fetch) cycle, used by
the Z80 for the decoding of the instructions fetched in earlier T periods, a
refresh signal is generated. the RFSH- terminal (pin 28) of the Z80 will go
LOW during this period. Note that this signal must be used in conjunction
with MREQ-, because RFSH- is guaranteed to be stable only when MREQ- is
active.

During the refresh period the lower portions of the address of a refresh
location is placed on the lower seven bits (A0-A6) of the address bus. (A7
is 0). The data on A0-A6 is frmo the R register in the Z80, which in
incremented after each instruction fetch. The upper 8 bits of the address
bus carry the contents of the I register.

 * * * * *

A block diagram follows in the book, which is much harder for me to type in.

Does that help ?

-Chris

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Chris Candreva -- chris@westnet.com -- (914) 967-7816
WestNet Internet Services of Westchester
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Received on Tue Jul 27 19:12:49 1999