RE: CCPU - Screenshots

Chris, the vector drawing is like you described. Here are a couple of
screen shots of my simulation. Lots of short vectors following by some
intense bursts at the end of the frame. The second picture is a bit more of
a close up.

http://www.cinematronics.org/images/ccpu_shot1.jpg
http://www.cinematronics.org/images/ccpu_shot2.jpg

> -----Original Message-----
> From: owner-vectorlist@vectorlist.org
> [mailto:owner-vectorlist@vectorlist.org] On Behalf Of Chris Schalick
> Sent: Tuesday, April 07, 2009 6:41 AM
> To: vectorlist@vectorlist.org
> Subject: Re: VECTOR: Cinematronics CCPU on Xilinx FPGA
>
>
> I got started on a Verilog CCPU a while ago, with the same
> structural approach. I got through a thousand instructions
> or so till it went red on me, summer showed up and I lost track of it.
>
> Much to my wife's chagrin, I speak Vhdl and would be happy to
> help verify if you want help.
>
> Chris
>
> --- On Tue, 4/7/09, Ed Henciak <ehenciak@yahoo.com> wrote:
>
> > From: Ed Henciak <ehenciak@yahoo.com>
> > Subject: Re: VECTOR: Cinematronics CCPU on Xilinx FPGA
> > To: vectorlist@vectorlist.org
> > Date: Tuesday, April 7, 2009, 3:55 AM
> > Freakin' sweet :-)! Your best QoR for area is going to be the gate
> > level approach you are taking. The tradeoff is "time to
> implement" in
> > most cases.
> >
> > Also, keep in mind that a behavioral design means exactly what it
> > says...it doesn't mean it is synthesizable.
> > Moreover, if anyone tells you one way is better than
> another they are
> > nuts. The example I sent you is more abstract (i.e. RTL)...what's
> > cool is that XST seems to do a decent job converting what I am
> > "implying"
> > when
> > I view the design using post-synthesis viewers. Still,
> area-wise, it
> > will be no match to your results. For designs like the CCPU, gate
> > level is the way to go....I prefer the RTL approach since that's
> > simply the way I do things :-)!
> >
> > Just a suggestion....goto www.fpgaarcade.com ... there is an
> > Asteroids-on-a-chip package. In there, MikeJ has a vector-to-VGA
> > converter. You will need to add a ZBT SRAM model to your design.
> > You might be able to pump out some graphics....just be
> aware that what
> > you see in simulation may not match expected results graphics wise
> > :-)!
> >
> > What version of Modelsim are you using BTW?
> >
> > Ed
> >
> > PS OK...bedtime for real...tomorrow is going to be a long day.
> >
> >
> >
> >
> >
> > ________________________________
> > From: Chris Leyson <cleyson@aol.com>
> > To: vectorlist@vectorlist.org
> > Sent: Tuesday, April 7, 2009 3:31:48 AM
> > Subject: VECTOR: Cinematronics CCPU on Xilinx FPGA
> >
> > Hi,
> >
> > Quick progress update, spacewars roms now modeled as block ram and
> > Modelsim is chucking out XY vectors :) About 80 to 90 vectors per
> > frame, most of them are really short, only 2us to 5us, I think they
> > might be stars.
> >
> > VHDL model is structural and a lot of it mimics the TTL on
> the CCPU,
> > it was the easiest approach given that I started with the
> schematic.
> > It was done this way so I could figure out how things worked. Don't
> > think the behavioral guys will like it :(
> >
> > Next task is to clock it properly then start replacing the
> TTL. ALU,
> > comparator and shifter should be easy and all of the data
> path logic
> > is just 2:1 muxes.
> >
> > Must get some ZZZs been up all night.
> >
> > Chris
> >
> ----------------------------------------------------------------------
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> > chris@westnet.com
>
>
>
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Received on Tue Apr 7 08:15:56 2009