Re: Another CCPU HDL model appears.

From: Chris Leyson <cleyson_at_aol.com>
Date: Sat Apr 18 2009 - 00:44:43 EDT

Zonn wrote:
> Hi Guys, I'm been *very* busy with company work as of late, but I do
> read all Vectorlist posts.
>
> Chris Leyson wrote:
>
>> Sure, there's room for several versions, Ed has been working on a
>> VHDL model for a while and is very
>> nearly there. Omar has, I think a VHDL model, Chris Schalick has a
>> Verilog model at TTL gate level.
>> Unfortunately both Omar's and Chris's models crashed and burned so to
>> speak. I've been crashing and
>> burning for the last week, thinking I was getting near to something
>> that worked, but it wasn't so.
>> Zonn may be working on a model, I don't know, but without Zonn's
>> excellent documentation of the CCPU
>> instruction set I wouldn't have got to where I am now. Thanks Zonn :)
> I can assure you I'm *not* working on a model of any kind. While
> Verilog and VHDL intrigue me, I've never touch any hardware modeling
> tools of any kind.
Sorry if I implied that you may have been working on an HDL CCPU. My
fault, I misinterpreted other peoples posts.
>
> I believe Ed sent me some stuff quite awhile ago, and I remember
> looking at it a thinking, wow, that's cool, I can almost understand this.
VHDL has a very similar syntax to C, constructs like "if then else"
describe "nano second" hardware rather than stepping through slow
sequential instructions.
Events trigger processes and you can describe as many processes as you
need. It's like parallel computing but at assembler level.
and of it goes.. done.
>
> My idea of a CCPU replacment board is one of those low cost ARM
> development boards, with some parallel I/O, running a perfect cycle by
> cycle emulation of the CCPU driving a ZVG.
CCPU carry flag does a few strange things so some work needed to
document the hardware.

> The sudden flurry of interest in the CCPU, is pretty dang cool!
>
> -Zonn
Thanks
>
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Received on Sat Apr 18 00:45:12 2009

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