Re: Cinematronics BPROM alternatives

Wow Ed!, You didn't have to go to so much trouble. Still appreciated
though! Actually, what I meant was that it wouldn't fit into the simple
PLD's, like 22V10 and such. My code did fit into the xc9536 CPLD. Mine
took 14% but I also included functional /g1 and /g2 enable inputs. My first
code list looked almost identical to the one that you provided. I saw an
example in a book for a lookup table structure so I wrote a new version
using that. It creates a constant array with all the data in it and then
runs a short process to copy data from the array to the outputs when enabled
and tristates the outputs when not enabled.

William Boucher
----- Original Message -----
From: "Ed Henciak" <ehenciak@yahoo.com>
To: <vectorlist@vectorlist.org>
Sent: Friday, October 09, 2009 6:10 AM
Subject: Re: VECTOR: Cinematronics BPROM alternatives

> OK, I whipped up the code attached below to test out the "bipolar prom in
> an XC9536XL-5-PC44".
>
> Basically :
>
> 4 of 36 Macrocells are used (12%)
> 0 of 36 registers are used (0% ... makes sense since this is a PROM).
> 12 of 34 pins used (4 data, 8 address)
> 16 of 108 Function Block Inputs used (15%).
>
> So it looks like it fits....for this PROM's pattern anyway. What I did
> was basically
> convert the binary for F14 on the CCPU board to text (through xxd using
> VI) and
> created the VHDL case statement below. Please do not confuse the case
> statement
> with a switch statement you might find in C. From a hardware perspective,
> think of
> a case as a multiplexor. I believe I recreated the proper data in the
> proper locations.
> I do not know if the PROM has outputs that invert what is stored in the
> array before driving
> out (this makes no difference ... simply invert the output).
>
> In ISE, I left all settings default. You should be able to set up a
> project and synthesize it!
>
> Here is the VHDL I synthesized ... feel free to use it.
>
> Ed
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity prom is
> port (
>
> addr : in std_logic_vector(7 downto 0);
> data : out std_logic_vector(3 downto 0)
> );
> end prom;
>
> architecture struct of prom is
>
> begin
>
> process(addr)
> begin
>
> case addr is
>
> when x"00" => data <= x"0";
> when x"01" => data <= x"0";
> when x"02" => data <= x"0";
> when x"03" => data <= x"0";
> when x"04" => data <= x"0";
> when x"05" => data <= x"f";
> when x"06" => data <= x"f";
> when x"07" => data <= x"f";
>
> when x"08" => data <= x"f";
> when x"09" => data <= x"f";
> when x"0a" => data <= x"e";
> when x"0b" => data <= x"e";
> when x"0c" => data <= x"d";
> when x"0d" => data <= x"f";
> when x"0e" => data <= x"f";
> when x"0f" => data <= x"2";
>
> when x"10" => data <= x"e";
> when x"11" => data <= x"e";
> when x"12" => data <= x"f";
> when x"13" => data <= x"f";
> when x"14" => data <= x"f";
> when x"15" => data <= x"f";
> when x"16" => data <= x"2";
> when x"17" => data <= x"2";
>
> when x"18" => data <= x"f";
> when x"19" => data <= x"f";
> when x"1a" => data <= x"f";
> when x"1b" => data <= x"7";
> when x"1c" => data <= x"7";
> when x"1d" => data <= x"7";
> when x"1e" => data <= x"0";
> when x"1f" => data <= x"0";
>
> when x"20" => data <= x"0";
> when x"21" => data <= x"0";
> when x"22" => data <= x"0";
> when x"23" => data <= x"0";
> when x"24" => data <= x"0";
> when x"25" => data <= x"0";
> when x"26" => data <= x"0";
> when x"27" => data <= x"0";
>
> when x"28" => data <= x"0";
> when x"29" => data <= x"2";
> when x"2a" => data <= x"e";
> when x"2b" => data <= x"e";
> when x"2c" => data <= x"2";
> when x"2d" => data <= x"7";
> when x"2e" => data <= x"2";
> when x"2f" => data <= x"2";
>
> when x"30" => data <= x"e";
> when x"31" => data <= x"e";
> when x"32" => data <= x"2";
> when x"33" => data <= x"f";
> when x"34" => data <= x"f";
> when x"35" => data <= x"f";
> when x"36" => data <= x"2";
> when x"37" => data <= x"2";
>
> when x"38" => data <= x"f";
> when x"39" => data <= x"f";
> when x"3a" => data <= x"2";
> when x"3b" => data <= x"3";
> when x"3c" => data <= x"1";
> when x"3d" => data <= x"1";
> when x"3e" => data <= x"0";
> when x"3f" => data <= x"0";
>
> when x"40" => data <= x"0";
> when x"41" => data <= x"0";
> when x"42" => data <= x"0";
> when x"43" => data <= x"0";
> when x"44" => data <= x"0";
> when x"45" => data <= x"e";
> when x"46" => data <= x"e";
> when x"47" => data <= x"e";
>
> when x"48" => data <= x"e";
> when x"49" => data <= x"e";
> when x"4a" => data <= x"e";
> when x"4b" => data <= x"e";
> when x"4c" => data <= x"e";
> when x"4d" => data <= x"1";
> when x"4e" => data <= x"e";
> when x"4f" => data <= x"2";
>
> when x"50" => data <= x"e";
> when x"51" => data <= x"e";
> when x"52" => data <= x"2";
> when x"53" => data <= x"2";
> when x"54" => data <= x"0";
> when x"55" => data <= x"0";
> when x"56" => data <= x"2";
> when x"57" => data <= x"2";
>
> when x"58" => data <= x"0";
> when x"59" => data <= x"0";
> when x"5a" => data <= x"e";
> when x"5b" => data <= x"7";
> when x"5c" => data <= x"7";
> when x"5d" => data <= x"7";
> when x"5e" => data <= x"0";
> when x"5f" => data <= x"0";
>
> when x"60" => data <= x"f";
> when x"61" => data <= x"f";
> when x"62" => data <= x"f";
> when x"63" => data <= x"f";
> when x"64" => data <= x"f";
> when x"65" => data <= x"f";
> when x"66" => data <= x"f";
> when x"67" => data <= x"f";
>
> when x"68" => data <= x"f";
> when x"69" => data <= x"f";
> when x"6a" => data <= x"f";
> when x"6b" => data <= x"f";
> when x"6c" => data <= x"f";
> when x"6d" => data <= x"f";
> when x"6e" => data <= x"f";
> when x"6f" => data <= x"f";
>
> when x"70" => data <= x"f";
> when x"71" => data <= x"f";
> when x"72" => data <= x"f";
> when x"73" => data <= x"f";
> when x"74" => data <= x"f";
> when x"75" => data <= x"f";
> when x"76" => data <= x"f";
> when x"77" => data <= x"f";
>
> when x"78" => data <= x"f";
> when x"79" => data <= x"f";
> when x"7a" => data <= x"f";
> when x"7b" => data <= x"f";
> when x"7c" => data <= x"f";
> when x"7d" => data <= x"f";
> when x"7e" => data <= x"f";
> when x"7f" => data <= x"f";
>
> when x"80" => data <= x"e";
> when x"81" => data <= x"e";
> when x"82" => data <= x"e";
> when x"83" => data <= x"e";
> when x"84" => data <= x"e";
> when x"85" => data <= x"f";
> when x"86" => data <= x"f";
> when x"87" => data <= x"f";
>
> when x"88" => data <= x"f";
> when x"89" => data <= x"f";
> when x"8a" => data <= x"e";
> when x"8b" => data <= x"e";
> when x"8c" => data <= x"d";
> when x"8d" => data <= x"f";
> when x"8e" => data <= x"f";
> when x"8f" => data <= x"e";
>
> when x"90" => data <= x"e";
> when x"91" => data <= x"e";
> when x"92" => data <= x"f";
> when x"93" => data <= x"f";
> when x"94" => data <= x"f";
> when x"95" => data <= x"f";
> when x"96" => data <= x"e";
> when x"97" => data <= x"e";
>
> when x"98" => data <= x"f";
> when x"99" => data <= x"f";
> when x"9a" => data <= x"f";
> when x"9b" => data <= x"e";
> when x"9c" => data <= x"e";
> when x"9d" => data <= x"e";
> when x"9e" => data <= x"e";
> when x"9f" => data <= x"e";
>
> when x"a0" => data <= x"e";
> when x"a1" => data <= x"e";
> when x"a2" => data <= x"e";
> when x"a3" => data <= x"e";
> when x"a4" => data <= x"e";
> when x"a5" => data <= x"e";
> when x"a6" => data <= x"e";
> when x"a7" => data <= x"e";
>
> when x"a8" => data <= x"e";
> when x"a9" => data <= x"e";
> when x"aa" => data <= x"e";
> when x"ab" => data <= x"e";
> when x"ac" => data <= x"e";
> when x"ad" => data <= x"e";
> when x"ae" => data <= x"e";
> when x"af" => data <= x"e";
>
> when x"b0" => data <= x"e";
> when x"b1" => data <= x"e";
> when x"b2" => data <= x"e";
> when x"b3" => data <= x"f";
> when x"b4" => data <= x"f";
> when x"b5" => data <= x"f";
> when x"b6" => data <= x"e";
> when x"b7" => data <= x"e";
>
> when x"b8" => data <= x"f";
> when x"b9" => data <= x"f";
> when x"ba" => data <= x"e";
> when x"bb" => data <= x"e";
> when x"bc" => data <= x"e";
> when x"bd" => data <= x"e";
> when x"be" => data <= x"e";
> when x"bf" => data <= x"e";
>
> when x"c0" => data <= x"e";
> when x"c1" => data <= x"e";
> when x"c2" => data <= x"e";
> when x"c3" => data <= x"e";
> when x"c4" => data <= x"e";
> when x"c5" => data <= x"e";
> when x"c6" => data <= x"e";
> when x"c7" => data <= x"e";
>
> when x"c8" => data <= x"e";
> when x"c9" => data <= x"e";
> when x"ca" => data <= x"e";
> when x"cb" => data <= x"e";
> when x"cc" => data <= x"e";
> when x"cd" => data <= x"e";
> when x"ce" => data <= x"e";
> when x"cf" => data <= x"e";
>
> when x"d0" => data <= x"e";
> when x"d1" => data <= x"e";
> when x"d2" => data <= x"e";
> when x"d3" => data <= x"e";
> when x"d4" => data <= x"e";
> when x"d5" => data <= x"e";
> when x"d6" => data <= x"e";
> when x"d7" => data <= x"e";
>
> when x"d8" => data <= x"e";
> when x"d9" => data <= x"e";
> when x"da" => data <= x"e";
> when x"db" => data <= x"e";
> when x"dc" => data <= x"e";
> when x"dd" => data <= x"e";
> when x"de" => data <= x"e";
> when x"df" => data <= x"e";
>
> when x"e0" => data <= x"f";
> when x"e1" => data <= x"f";
> when x"e2" => data <= x"f";
> when x"e3" => data <= x"f";
> when x"e4" => data <= x"f";
> when x"e5" => data <= x"f";
> when x"e6" => data <= x"f";
> when x"e7" => data <= x"f";
>
> when x"e8" => data <= x"f";
> when x"e9" => data <= x"f";
> when x"ea" => data <= x"f";
> when x"eb" => data <= x"f";
> when x"ec" => data <= x"f";
> when x"ed" => data <= x"f";
> when x"ee" => data <= x"f";
> when x"ef" => data <= x"f";
>
> when x"f0" => data <= x"f";
> when x"f1" => data <= x"f";
> when x"f2" => data <= x"f";
> when x"f3" => data <= x"f";
> when x"f4" => data <= x"f";
> when x"f5" => data <= x"f";
> when x"f6" => data <= x"f";
> when x"f7" => data <= x"f";
>
> when x"f8" => data <= x"f";
> when x"f9" => data <= x"f";
> when x"fa" => data <= x"f";
> when x"fb" => data <= x"f";
> when x"fc" => data <= x"f";
> when x"fd" => data <= x"f";
> when x"fe" => data <= x"f";
> when x"ff" => data <= x"f";
>
> when others => data <= x"0";
>
> end case;
>
> end process;
>
> end
>
>
>
>
> Clay Cowgill wrote:
>>> I have also designed a replacement for the larger BPROM (74S287 256 x 4)
>>> located at F14. For a first effort, it is based on a Xilinx XC9536. I
>>> couldn't get all of the data to fit into a cheaper SPLD but I'm open to
>>> suggestions if someone has a smaller cheaper chip in mind for the job.
>>>
>>
>> What did you try to fit that in, SPLD-wise? (22V10?) I have a crapload
>> of
>> 26V12's in PLCC if the Atmel stuff can target that. (I don't think they
>> ever made one though.) How close is CUPL To ABEL? I could try fitting
>> it
>> with my old Lattice software into the 26V12 if you wanted.
>>
>> -Clay
>>
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>>
>>
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Received on Fri Oct 9 11:11:10 2009