Re: FPGA

On Tue, 7 Oct 1997 09:15:34 -0700, you wrote:

>G'day folks,
>
>So as long as we are out on RAM tangents, can I ask if there's a 4:1
>ration of DRAM to SRAM how does the recent IBM (or was it Intel) memory
>breakthrough of 2 bits per "memory cell" affect this ratio? Can I
>assume that it just brings SRAM storage capacity closer to DRAM storage
>capacity?

This "breakthrough" was bit bogus I thought. It only applies to Flash
EEPROM, and isn't much of a breakthrough, though it could aid in higher
density EEPROM.

EEPROMs use a storage cell that acts like a permanently charged capacitor.
In the past the capacitor was either charged, or discharged, a one, or a
zero. Intel is now charging the capacitor to 4 different levels
representing 00, 01, 10 and 11.

It's a neat approach but why isn't it much of a breakthrough? Go to Radio
Shack and buy one of those "record your voice chips". That company was
getting some great compression ratios, so I looked into what they were
doing. It turns out they're recording analog information into each EEPROM
cell. By recording 256 different levels into each EEPROM cell they're able
to store 8 bits of information into each cell, allowing for an 8:1
compression ratio, with little loss, using 8 bit data. Pretty cool, to bad
it only works for EEPROM. I'm assuming the absolute accuracy of each
stored values is not good enough for digital storage (or Intel would be
claiming 8 bits per cell), but is close enough for audio.

These chips have been out for quite awhile, by this time it's no longer a
"breakthrough". In an article I read, the extra glue logic needed to read
and write two bits per cell keeps Intel's new memory from being much
denser, but they're working on it (I'm sure they'll get something going, it
seems like a nice way of getting more storage out of flash EEPROM).

-Zonn
Received on Tue Oct 7 12:28:45 1997