On Wed, 17 Dec 1997, Paul Kahler wrote:
> Funny, if we used serial DACs we might as well go ahead with Al's idea to
> do serial addition. Then all we'd have is some registers shifting around
> through 2 or 4 1-bit adders and out to the DAC. WOW! Now 24 shifts at
> 3-4 times the asteroids clock speed is probably too fast for anything cheap.
> Can the PLD run at ~100MHz?
>
I know some Altera stuff can. Back when I took the standard
"Build a Microprocessor from TTL and PLDs" course, There were some Altera
parts which were as low as 5 ns.
Actually I've been thinking about something.....
Clay, what parts were you targeting to when you posted about your
original adder? A Xilinx CLB can implement any function of 5 variables,
so a 24 bit ripple-carry adder would take < 48 CLBs, which seems pretty
reasonable to me. It might suck up a lot of routing resources, though...
Joe
Received on Wed Dec 17 15:43:05 1997
This archive was generated by hypermail 2.1.8 : Thu Jul 31 2003 - 23:01:05 EDT